EP0109963A1 - Device for editing picture carriers of television signals - Google Patents

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Kind code of ref document: Country of ref document: Date of ref document: Year of fee payment: Ref legal event code: The invention relates handel binare signalent a device for the image carrier processing of television signals by phase-locked coupling of the picture carriers by means of linking the individual picture carrier frequencies in each case a reference frequency and by a defined frequency offset between these signals with one of a phase comparison circuit, a regulated in its frequency of this oscillator and a controlled therewith mixer existing PLL circuit, wherein the Phasenver - the same circuit for one of the out of the respective payload - handel binare signalent derived TV standard IF signal and the other of the offset by the heat generated by a respective generator offset frequency from the mixer from the oscillator signal is actuated and a reference signal obtained reference IF signal.

Institutions represented in principle 1 are known from the magazines publications "Improving the cable television transmission by an optimal coherent support system" broadcast Technical CommunicationsH. They serve to reduce the impression of interference that results from single channel reception by co-channel interference for example, direct irradiation of the local transmitter signal in the receiver or by ranges of adjacent transmitter and for multi-channel transmission due to nonlinear distortion, for example, in stretching - amplifiers of broadband cable networks.

According to these two use cases, either the local transmitter signal or, depending on a particular frequency processing device as the reference signal source for the or the image carrier of each channel is used. The trouble-reducing measures the phase-locked carrier - handel binare signalent and frequency offset allow for multi - channel transmission either an increase in channel allocation, so the program capacity in existing networks or increasing the length of the route with the same number of amplifiers and thus reduce costs.

This object is solved by DAB each of the handel binare signalent inputs of the phase comparison circuit is connected upstream of two same digital frequency dividers and one of them in such a manner controlled by the offset signal a, to be part of factor dAb changed in time with the offset signal.

The use of a digital frequency divider in a PLL circuit, although, for example, from the book "radio technology without ballast" of 0. Aeschlimann, Franzis-Verlag, 12th editionp. Im Gegensatz dazu wird der Teilfaktor des vom Versatzsignal angesteuerten Frequenzteilers bei der Erfindung im Takte des Versatzsignales umgeschaltet zB von 40 auf 41 bzw.

In contrast, the division factor of the driven from the offset signal frequency divider is switched in the invention, in time with the offset signal for example, from 40 to 41 or vice versawherein the phase comparison handel binare signalent compares the different period of the two digital divider output signals with each other and generates the pull voltage for the oscillator.

This regulates by until the reference IF, and thus the frequency of the output signal is changed to the device exactly handel binare signalent the offset frequency in a desired manner. Der Frequenzteiler wirkt somit zugleich als Addier- bzw. The frequency divider thus also acts as adder or subtractor, while in use of frequency dividers with a fixed division ratio of such a component is also needed. AuBerdem is the device of the invention in the position, in contrast to the known SSM, which because of its Frequenzab - dependence be retuned for each frequency offset, to process MUB offset frequency deviations of wideband 0.

Moreover, is the operating frequency range of Phasenver - the same circuit as deep with the use of frequency dividers with practically meaningful part factors Dab cheap CMOS devices are used instead of the required in the prior art expensive discrete circuits or ECL modules.

The invention described in Claim 1 means the oscillator of the PLL changes its frequency in time with the offset signal, whereby the wanted signal is frequency-modulated at the output of mixer. To avoid this undesirable effect, as indicated in claim 2 advantageous embodiment of the invention is a pre between phase-comparison circuit and oscillator is switched TiefpaB with appropriate time constant - see. The determination of the size of the two factors apart from the desired output frequency range of the frequency divider and which determines DAB less handel binare signalent switched with increasing difference between the partial factors of handel binare signalent frequency divider in question and the realization handel binare signalent the time constant of the low-pass filter thereby becomes increasingly difficult.

It is therefore advantageous, the highest possible frequency of switching from one part handel binare signalent the other factor and thus to choose the smallest possible integer difference between the partial factors for a given offset frequency.

The embodiment of claim 3 provides for an optimal solution. This own reference treatment is no longer necessary as before for each channel. A particularly expedient embodiment of this cost reference signal source is described in claim.

At the output of the device, the picture carrier frequencies are characterized with standards generated in the CCIR-grid on both simple and elegant manner. The frequency of handel binare signalent MHz is not necessarily generated by an oscillator, it can rather emitted in a simple manner by an example of standard frequency transmitters Leitfre - are derived sequence.

An alternative to this embodiment of claim 5 defined in claim. With her, the frequency divider to generate the kHz signal is saved, but however, the comb generator consuming. In individual cases for each channel, an individual offset ge - wishes, this is according to claim 7 readily by switching an offset signal either via an adder to the possible reference IF branch or directly to the in-ZF-branch frequency divider.

The image carrier-conditioning device according to the invention is suitable in particular due to the formation according to claims 1 and 4, in contrast to handel binare signalent prior art for the application and inexpensive construction in a modular system. For this example, the following blocks are: This handel binare signalent it possible, the processing device to a - to modify ways according to the needs of the individual case either for connection to the local station or Frequenzverkopplung in multichannel systems, both in harmony and in incremental coupling, with or without offset optimal.

Dadurch ist sowohl die Anwendung als auch der Schaltungsaufwand vereinfacht. Result, both the application and the circuitry is simplified. Dabei zeigt i Fig. The most important signals of this circuit in a pulse diagram. At the handel binare signalent E of an unillustrated Eingangsum - handel binare signalent 20 setter, is coupled out through a tap per 1 - stays awhile picture carrier IF signal is in a PLL control loop to a corresponding, from the mixer 2 of the PLL circuit from handel binare signalent reference picture carrier signal derived by an offset staggered in the frequency reference picture carrier Handel binare signalent signal phase 25 rigidly coupled and converted back to an output converter 3 in the picture carrier frequency located at the handel binare signalent a, wherein the mixer 4 of the output converter 3 between input e and output A is turned on and the oscillator 5 operates at the same time as the control oscillator of the PLL circuit.

Without offset signal frequency dividers 7, 8 the division factor 40 have, so that at the inputs the phase comparison circuit 6 first signals of the frequency. Is now in one handel binare signalent the two frequency divider is fed in the present embodiment in the past in the reference branch frequency divider 7, a displacement signal, then the division factor of this displacement handel binare signalent changes in cycles of 40 to In each of switching to the part of factor 41 is handel binare signalent output signal period of this frequency divider 7 is larger than that of the other frequency divider 8 so that is adjusted by the PLL circuit.

While avoiding a switched between phase comparison circuit 6 and the oscillator 5 low-pass filter 11, that the handel binare signalent frequency at the clock rate of the displacement signal changes, and the image carrier - the output signal is frequency-modulated thereby.

As stated above, the realization of the time constant of this low-pass filter 11, the higher the easier the switching frequency of the Sub-factor. The described switching of the sub-factor is the after - pull the oscillator frequency and thus the here desired positive or, wherein feeding of the offset signal in the other frequency divider 8, negative handel binare signalent offset of the image carrier-off - crossing signal by the offset frequency without the use handel binare signalent a sub - trahiergliedes or, with a negative frequency offset of an adder realized.

This saving results in a further effort and cost - reduction of in itself prepared from commercially handel binare signalent IC's cost digital frequency divider 7.

Als Referenzsignalquelle 12 ist ein hochgenauer 1-MHz-Oszillator 13 mit nachgeschaltetem Kammgenerator 14 vorgesehen. As a reference signal source 12, a high-precision 1-MHz oscillator with a downstream comb generator 14 is provided. The mixer 2 of the PLL circuit only signals handel binare signalent supplied so that, however, the frequencies of which are integer multiples of 1 MHz.

So that all relevant television picture carrier frequencies are generated with a single reference signal source advantageously. For a better understanding of the operation is first of a circuit according to Fig understood 3, in which the unimportant for explaining the principle operation of Beschal. With the aid of the second JK flip-flop 20, the switching signal e for the divider IC 18 with the output signal d is synchronized. Since the switch signal e d must be stable during the HL-edge of the output signal, the acquisition of the second flip-flop 20 is made on the LH-edge of the output signal d.

The system will remain in this state until the JK flip-flop 19 by the next LH-edge of the offset signal c it - is set neut. The individual circuit elements are summarized in the following, for the construction of treatment facilities for all television image carrier and different offset frequencies suitable modules: The limiter 9 in the reference branch of the phase comparator 22 is true when using a reference signal source 12 be governed according to the embodiment is not necessary, but it makes the handel binare signalent 22, regardless of the type of handel binare signalent signal source 12 handel binare signalent generally used.

The same applies to the mechanical switch 24 of the offset generator 23, via which the offset signal on one of the two frequency dividers 7, 8 is switched, depending on whether a positive or negative offset is to take place. That form part factor in time with the offset signal changed. Device according to claim 1, characterized in that the DAB between phase-comparison circuit 6 and the oscillator 5 a low-pass filter 22 is switched whose time constant is sized DAB, the oscillator frequency is not changed in time with the offset signal.

A device handel binare signalent to any one of claims 1 to 3 characterized in that a single reference signal source 12 is provided for generating the reference signals of all television channels reprocessed. A device according to claim 4, characterized in That the reference signal source from a high-precision 1-MHz oscillator 13 with a downstream comb generator 14 and DAB from the 1-MHz oscillator 13 by means of a frequency divider 15 is kHz signal derived and between the mixer 2 and phase comparison circuit 6 inserted frequency divider 7 is fed.

Einrichtung nach Anspruch 4, dadurch gekennzeichnet, daB die Referenzsignalquelle aus einem kHz-Oszillator mit nachgeschaltetem Kammgenerator besteht. A device according to claim 4, characterized in That the handel binare signalent signal source consists of a kHz oscillator with a downstream comb generator. A device according to claim 5, characterized in Dab the kHz offset signal via an adder 16 or between phase comparison circuit 6 and IF AnschluB 1 the switched-divider 8 directly an offset signal supplied.

Device according to claim 8, characterized in that the DAB an EXOR gate 21 having its inputs connected between the outputs D of each frequency divider 7, 8 and the second flip-flop 20 is connected and actuates this to its output signal. EP EPB1 en DE DED1 en Method and apparatus for reducing distortion in multicarrier communication systems.

JuliSeitenBerlin, DE. Impulssignalverzoegerungsvorrichtung, pulse signal phase detector and the apparatus used Direction clock generator.

Frequency division circuit for non-integer divisors after the manner of a rate multiplier. Integrated digital filter circuit for the luminance channel of colour television sets. Software clock operating method for electronic entertainment appts. Horizontal scanning phase control circuit for video monitor - includes two monostable multivibrators, one operated by return flanks of horizontal synchronising pulses.

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Kind code of ref document: Country of ref document: Date of ref document: Year of fee payment: Ref legal event code: The invention relates to a signal processing device for each channel time switch and including a device for feeder routes both in call mode call in reserved mode. The exchange which contains at least the control units UC and terminal units UT , a microprocessor and a switching network RCX to which the units UA, UTI are connected by bidirectional multiplex links MU includes a terminal unit brewing UTB receiving the signaling pathways associated with the communication channels for which a reservation is requested and ensuring the mixing of these signaling pathways and their retransmission to their destinations via the switching network.

The terminal units UTI of digital circuits, connected to temporal MIC junctions which serve the PABX, will handle the signaling and synchronization link communication with the brewing unit. The invention relates to telecommunications. It is particularly applicable in a telephone exchange with digital lines operated by call calling mode and digital lines operated in reserved mode.

In such a central, it is usual to connect a line or an input circuit to a line or an output circuit through the switching network, the signaling being received and transmitted under the control of the central control bodies.

In the case of dedicated lines can not, as in the old analog systems, directly connect the incoming line to the outgoing line permanently during the lease term of the line.

So we established semi-permanent connections in the connection network for dedicated lines, and signals received in the same way as for lines operated per call is re-emitted in connection network output so that the central is transparent to the dedicated lines, and the renter has complete freedom to use the signaling channel assigned to it.

This procedure has drawbacks that the management of the signaling leased lines mobilizes a part of the throttle, and secondly the fact that full transparency is binding. Accordingly, the object of the invention is to provide a device realizing a processing signaling pathways call by call, and a simple referral signaling for dedicated lines. The present invention therefore provides a channel associated signaling processing device to switch comprising microprocessor control units, microprocessor terminal units, a switching network and wherein the control and terminal units are connected to the network connection by bidirectional multiplex links ensuring the placing in communication of the terminal units on the one hand to each other, on the other hand with the control units that drive.

According to one feature of the invention the signal processing device comprises means for the serving of voice channels as call by call mode in reserved mode, the units of digital circuit terminals each serving a temporal MIC junction comprising For this purpose in each digital circuit: The present invention, its advantages and features are specified in the following description in conjunction with the figures below referenced: Figure 1 shows a diagram of a switch incorporating the invention.

Figure 3 shows a brewing unit according to the invention. Figures 4A, 4B show a digital terminal according to the invention. The figure shows a signal receiving circuit according to the invention. The time-division switching network RCX is preferably of the type described in French patent application No.

The switch of the control system is preferably of the type described in French patent application No. Each CU control unit essentially comprises a microprocessor connected by bus connections to memories and specialized interfaces binding. The UCP peripheral control units have almost same structure as the unmarked control units UC, they are differentiated by the fact that they contain specialized couplers, not shown here, for specific devices, such couplers for PF1 and PF2 disk interface terminal in the case of the peripheral control unit UCP1 and couplers for a magnetic tape drive PF3 and PF4 for an operator terminal for UCPF peripheral controller.

A base BTG general time provides the clock and synchronization signals required for operation of the switch, it is for example of the type described in Patent No. MD distribution modules are independent of each other, they are divided distribution of clock and synchronization signals to the CPU control units and terminal units UT and comprise for this purpose a non-represented here logic which allows them to each of selecting a pair of two signals one clock, the other synchronization among the pairs of signals provided by the base BTG general time.

Each clock circuit and synchronization CBT receives the clock and timing provided by two distribution modules signals MD, via base connections time referenced generally LBT, to bring these signals available to control units UC of a GUC group or terminal units UT of a GUT determined group, it being understood that the terminal units UT are also rassem - blies GUT by groups comprising at least one and usually several terminal units.

Each clock and timing circuit is further interposed for synchronization purposes on multiplex links generally referenced MU which connect the terminal units of a GUT group or the control units LCUs a group switching network RCX for the exchange of messages between units, each LCU or GUT group being connected to each RX plane of the switching network by a link multiplex different MU.

The terminal TN ensures both the interface between the received time MICR link and an outgoing multiplex link LT38 and also the interface between an input multiplex link and the emitted LTE8 temporal connection MICE it comprises this purpose specific circuits either of the transmission directions and a common circuit choice of clock signals and synchronization CES. The ESC selection circuit of a digital circuit terminal unit UTI ensures the selection, the microprocessor MP1 of the control unit, signals transmitted by one of two clock signal connections and HS1 synchronization and HS2 which the unit is connected.

In addition a rest code generating circuit ECR is connected to a LTS7 output multiplex link for transmitting a break code on unused channels on the order of microprocessor MP1 unit UTI terminals that includes the at rate set by the clock and synchronization signals transmitted by the CHS selector circuit.

The synchronization circuit and signal SES essentially comprises a SM multiframe synchronization analysis device connected at its input to an input multiplex link LTES, a synchronization circuit connected to the RB SM multiframe synchronization circuit and to the input multiplex link and providing resynchronization signals from the UTB brewing unit relative to aul- titrame local signal and a signal transmission circuit connected to the RB ES synchronization circuit and connected by its output to an output multiplex link LTS5.

Insofar LTE bonds, LTS, HS are identical to those described in relation to the unit of digital terminals UTI, and or the clock and synchronizing circuit CBT is also, these links and this circuit included with the same references and will not be redefined, without exception. At a maximum capacity BR Brewer is able to brew signaling nibbles.

BR brewer also manages the multiframe synchronization, because if the signaling pathways from different digital circuits CN were synchronized at the frame, the position of the frame alignment signal is one in BR brewer input.

To account for the orders of brews, which include a channel number and a frame number, the BR brewer must: For all the characteristics relating to the frames and multiframes we refer in particular to notice G of the CCITT.

For unused channels, the brewer must also issue a rest code. The brewing memory MT contains words of one byte. Outputting the memory is read by the quartet and bytes to be transmitted are composed of an injection circuit INJ connected to the output multiplex link LIS by a parallel to serial converter PSC.

A sequencer SQ, whose period is a multiframe, receives the HS link signals and distributes synchronous channel address signals with the reference signal mentioned above, and the signals s1 to sn sequencing the internal operation of brewer BR.

For brewing, brewing MT memory is addressed through a multiplexer MX Figures 4 to 7 the following possible to specify the circuits involved in the implementation of the present invention, it is noted that in the following description is optionally called door, a set of identical elementary gates controlled identically.

The instant loading controlled through P8 holder is fixed by a synchronization device connected to one of the inputs of this gate P8, it is determined by the synchronizing signal SY applied to a flip-flop whose output B7 feeds a shift register RD1 whose output is connected to the input of above mentioned gate P8.

Loss of synchronization on the received time MICR binding is shown by the appearance of a succession of bits of a value at the output of this binding. The condition for an alarm is that there are fewer than eight bits in the zero state in a frame, this is controlled by means of a shift register RD2 connected LME connections from WD and the transcoder TR via a P10 type aND gate and a latch B8.

This register RD2 is read by the microprocessor MP1 of the unit of UTI terminals via a type of AND gate P11 whose output is connected to the data bus BD1, one input of which receives a read enable signal VL3 and the other input receives the signal from the shift register RD2, via an inverter I2 in series with a flip-flop B9 connected by its inputs the output of the register RD2 and B7 latch.

The three bit TIV odd frame alignment signal, may also be positioned one by the TN digital terminal via an OR gate P16 connected to an input of multiplexer MX2, when frame locking loss. P16 gate receives on the one hand the frame locking loss signal provided by the inverter I1, is connected on the other hand the output of the register RE4.

As mentioned above, on the order of a microprocessor MP1 break code is continuously transmitted on the output multiplex link LTS7 by a usual ECR circuit controlled by the signals SY and W so as to occupy the unused time slots by the digital TAB terminal. The synchronization circuit and signal SES presented in Figure 5, comprises essentially as described above a multiframe synchronization mark SM device, a synchronization circuit RB CB brewer signal relative to the local multiframe signal and an ES signal transmission circuit.

Ce circuit de synchronisation et de signalisation SES permet de traiter des supermultitrames de quatre trames, permettant d'augmenter le nombre de canaux de signalisation en voie de signalisation seize. This synchronization circuit and signal SES can treat supermultitrames four frames to increase the number of track signaling channels sixteen signaling. Indeed, a normal frame with a sixteen channel bit of a frame corresponds to a Hz channel, while with the supermultitrame mentioned above a sixteen channel bit of a frame provides a channel Hz, two channel or four channels Hz to Hz for a multiframe.

The multiframe synchronization is searched sequentially for channel signals from a received time binding and MICR to the channel signals from a brewer CB. For this temporal connection matrix CX1 needle signaling from the received time binding MICR on the thirty channel and one of the input multiplex link and the signaling LTE5 reserved on the track fifteen of the same LTE5 bond.

The phases of internal operation of the ITS synchronization and signaling circuit are determined by a binary counter CR1 controlled by the W clock signal and synchronized by the SMT multiframe synchronization signal via a set of gates P17, P18, P19, P43 aND type and a duly combined inverter I3.

The binary counter CR1 has fourteen bits for identifying using three bits CO-C2 bit number, using five bits C3-C7 a time slot number and using four bits C8 C11 to a frame number in a multiframe identified itself in a supermultitrame by two bits C12, C Les phases de fonctionnement du circuit de synchronisation et de signalisation.

Les principaux signaux fournis par le circuit CLP1 sont: The main signals provided by the CLP1 circuit are: Les principaux signaux fournis par le groupe de bascule GB1 sont: The main signals provided by the flip-flop group GB1 are: The fifth bit is referenced 4 for signaling the non reoon- birth of the alignment word in a first frame multiframe. The sixth bit is referenced 5 for signaling that the received byte is composed of zeros, it is updated every frame irrespective of the state of the locking and is used to detect bit time slot zero IT16 signaling for one or two successive multiframes and upon resumption of the multiframe alignment signal to indicate that the previous time slot TS16 is received with at least one bit value a.

The seventh referenced bit 6 indicates the loss of multiframe PVMT lock after receiving two locking erroneous multiframe.

The eighth referenced bit 7 indicates a treatment of last frame multiframe. The first seven bits of multiframe alignment signal are stored in a status register RE5 for processing signaling from the temporal connection and received MICR RE6 in a status register. The locking paging signals multiframe RMDL and LDB selectively provide for validation of the M1 latch memory, via a type P24 OR gate the inputs of which they are applied and selective validation P21 doors and P23 located at the output the a status register RES, the other register RE6 state, and connected to the addressing inputs of the memory M1 locking.

Thus in each search cycle multiframe alignment, the addressing of the memory M1 locking for the development of a new status word consists of the following bits: The microprocessor MP1 of the terminal unit UTI controls the transmission of the signal to the synchronization circuit and signal SES at times desired to allow a storage in the RD4 signaling register. Similarly, two quartets issued by a CB brewer are received by the register RD4 during time slot IT15 of the sixteenth channel under the control of DEB signal applied to the gate PO and both bits 7 and 8 provided by the corresponding decoder of DEZ zero state are set M1 latch memory in the signal LDB controlled iT30 the time interval corresponding to the penultimate weft path.

The VMT multiframe locking is considered lost when both blocking signals are sueeessivement received erroneous. In this case the multiframe locking TMV is searched for in the second frame TR and TR15 in the penultimate frame to ensure that there is no double or input frame hopping TN digital terminal before is reported loss of multiframe alignment.

The multiframe alignment is also considered oomme lost when all the bits of the signaling pathway are in the zero state for a period corerespondant to one or two frames. The multiframe alignment is considered taken in detecting at least one bit in state one in the IT16 channel time interval which precedes the first multiframe alignment signal detected. A group of six flip-flops B11 B16 information used to store the passage of the last frame of a multiframe and to give the alarm to the microprocessor MP1 by sending a IN4 interruption, the latches B11, B12, B15 and B16 are selectively connected in M1 latch memory output by their inputs and all six flip-flops is controlled in the manner discussed below.

The signaling transmitter is performed by the ES transmission circuit using a broadcast memory M2 of the RAM type wherein the Ml microprocessor UTI terminal unit can write words containing commands which are especially: The orders consist of sixteen bits here split into two bytes one lightweight and one of most significant.

The low byte and the first four bits of the most significant byte corresponds here to the signal transmission time, the fifth bit or bit 4 corresponds to the state of transmission in bit, the sixth bit is masked and indicates when it is zero the channel is reserved to signals from the brewer.

The seventh bit indicates an interrupt signal and the eighth bit indicates the state of the bit to be transmitted given the mask and the brewer. MX4 multiplexer whose input selection is controlled by a mask bit 13 contained in register RES, has two inputs one connected to shift register output RD5 the other receiving a bit 12 of the register RES. The multiplexer MX5 is cyclically controlled by the count signals provided by the counter CR1, which provides the addressing of the broadcast memory M2 every four channel time intervals to form an eight bit word to be transmitted in the signaling channel TS16 on the transmitted temporal connection MICE served by the unit of UTI terminals considered.

There double reading of the sending memory M2 in each PCM signal cycle since the transmission orders comprise two bytes, this reading is performed under the control of LDFO read signals for one and LDFA for another which correspond each to a state of the bit 1 of the counter CR1.

The duration of transmission of a signal is determined by the DES down counter that receives twelve bits for this purpose. In order two doors P29 and P30 share distribution they countdown the twelve-bit DES are inserted into output of another P28 also door type and which is connected to M2 memory output and are controlled respectively by one LDFA read signal and the other by the other LDFO read signal.

The down counter is decremented if the OF bit 11 which is the transmission duration of significant bit is in state a, corresponding to a time-limited transmission order, it is in zero state the emission is cyclic with each multiframe for an unlimited duration by counting.

The register RES stores bits of the high byte. The counting status bit to be transmitted which is set by bit 15 of the transmission order is stored in a transmit register RE7 controlled output by a clock signal HE.

The modified data in the down DES and RES register are introduced into the broadcast memory M2 at the same address as the data that gave them birth, the counter CR1 with ongoing C5 to C13 outputs in the same state. In the case of signaling from the brewer BR, M2 sending memory is addressed by the counter CR3 controlled by the clock signal H2 applied to an AND gate P36 controlled by the complement of the last T15B frame signal which is provided by a I13 inverter, the counter CR3 is synchronized by the last T15B frame signal applied to a gate P.

Reading the broadcast memory M2 is controlled either by a C bit output of the counter CR1 or by the LEC signal from the microprocessor MP1, one and the other being applied to a type OR gate P39 whose output is connected to an input of the type of aND gate P28 which is connected in M2 sending memory output and which is controlled by the signal LM. A logic circuit formed of LO not figured latches is connected to the outputs of the down counter and the OF register RES, it allows to issue an interrupt to the IN3 CIP1 interrupt comprises a decision circuit of the microprocessor MP1 at the end of issuance a signaling bit.

The control register RE10 is connected by its outputs to the memory M1 for test purposes, a reset input of the alarm latches BB16 and the bus BD1 via a type of gate P42 controlled analogously to P40 door. GIS signal receiving circuit shown in Figure 6 receives the signaling transmitted in sixteen channel temporal link received MICR, on referral of the microprocessor MP1 and via the input multiplex link LTE6, it ensures the detection of bits of the status changes of signaling and transmission confirmed changes to the MPL microprocessor.

The signaling from the channel corresponding to the slot 16 of the time interval binding MICR received via the input multiplex link LTE6 for a reserved line is firstly transmitted to a receiver shift register to RD6, secondly a RD7 transmitter shift register via an OR gate type P40, the output of this register RD7 transmitter supplying the output multiplex link LTS6. The receiver register RD6 control input is controlled by a type of AND gate P50 which receives the complement of the clock signal W and one of the enable signals Vi supplied by the logic unit CLP2, register of the control input RD7 transmitter also receives the complement of the clock signal W supplied by the CHS clock selector circuit.